Integrated circuits (ICs), including memory devices such as dynamic random access memories (DRAMs) require testing to enhance the ability of the user of such parts to determine the integrity of, or to characterize, the devices. Such testing may be implemented through test modes that include special tests, measurement functions, or algorithms to provide the user with such integrity or characteristics of the devices being tested. Test modes are utilized to test devices as opposed to operational modes which, for example, alter the operational characteristics of the device and which are intended to be used in system operation. For example, in operational mode, operational characteristics of a DRAM would be altered, but such alteration would not interfere with the DRAM's function as a storage device. For DRAM devices, Jedec Standard No. 21-C defines a scheme for controlling a series of special modes for the address multiplexed DRAMs and the logic interface required to enter, control, and exit the special modes. In addition, it defines special test and operational modes.
The Jedec Standard No. 21-C provides that special modes are to be initiated by a clock sequence called "write enable and column address strobe (CAS) before row address strobe (RAS)," which may be referred to as a WCBR clock sequence. The WCBR sequence is shown in FIG. 3 herein. When this clock sequence is generated, the state of address keys define a test mode or operational mode to be selected. The mode is latched and remains in effect until a release cycle is generated, or a new initiating cycle defining some other mode is generated. Following the initiating cycle, all subsequent cycles except for refresh cycles will be operating cycles as allowed by the mode selected. As further provided in the Jedec Standard, the test modes are cleared and the memory device returned to its normal operational state by application of any normal refresh cycle, for example a "RAS only refresh," or a "CAS before RAS refresh (CBR)." The Jedec Standard No. 21-C describes various other testing functions, and the standard is herein incorporated in its entirety by reference thereto.
Prior memory devices, such as DRAMs have utilized WCBR supervoltage cycles for initiation and control of test modes. For example, test modes are entered via an address input of the memory device by applying a supervoltage to a supervoltage pin while performing a WCBR cycle. The test mode address vector for the test mode to be selected is applied to the address input and used to configure each test mode. The test mode selected and entered is then valid as long as the supervoltage is applied. As long as the supervoltage is applied to the supervoltage pin, additional test modes can be entered via the address input during subsequent WCBRs. If the supervoltage applied is removed, all selected test modes are cleared. A CBR and RAS only refresh will not kick you out of the selected test modes. Only removing the supervoltage from the supervoltage pin will clear all the selected test modes.
There are various circumstances which decrease the reliability of initiating and controlling various test modes for testing integrated circuits, in particular memory devices such as DRAMs. For example, during powerup, or during power supply surges, there is a possibility of accidentally entering test modes when it is not desired to enter such test modes. Further, without adequate safeguards, test modes as opposed to other modes such as operational modes may also be accidentally entered when undesired. Present devices do not include adequate safeguards and therefore, there is a need in the art to provide such safeguards to increase the reliability for operation of the test modes and the testing process.